The present invention relates to a behavioral synthesis apparatus, a behavioral synthesis method, a data processing system including a behavioral synthesis apparatus, and a non-transitory computer readable medium storing a behavioral synthesis program.
The development of a behavioral synthesis apparatus that automatically generates a code of a circuit structure (structural code) such as an RTL (Register Transfer Level) code from a code of a circuit behavior (behavioral code) by using a C-language or the like has been underway. In recent years, in particular, it has been desired to develop a behavioral synthesis apparatus capable of generating an RTL code with a high throughput (processing capability).
Japanese Patent No. 4770657 discloses a related art. A pipeline synthesis system disclosed in Japanese Patent No. 4770657 generates an RTL code that performs a pipeline operation from a loop description included in a behavioral code. In this way, this pipeline synthesis system generates an RTL code that reduces the number of execution cycles and thereby achieves a high throughput.
The RTL code generated by the above-described behavioral synthesis apparatus is converted into an object code through placing/routing processing and the like. Then, the converted object code is used as a circuit for an FPGA (Field Programmable Gate Array) or for a rewritable programmable device such as a dynamically-reconfigurable processor.
Japanese Patent No. 3921367 discloses a related art. A parallel arithmetic apparatus disclosed in Japanese Patent No. 3921367 changes a context (operating state) for each state based on an object code supplied from a data processing apparatus and operates a plurality of processing circuits in parallel. This parallel arithmetic apparatus can reconfigure the plurality of processing circuits according to the state (i.e., can dynamically reconfigure the plurality of processing circuits). Therefore, this parallel arithmetic apparatus can execute complex processing with a small circuit scale.